Job Details

Be part of the Cadence DDR PHY IP Front End Design team responsible for - - Develop firmware for DDR 5 PHY using microcontrollers - Developing firmware in C typically involving bare-metal programming and developing low-level APIs on Microcontrollers. - Responsible for collaborating with hardware designers and memory subsystem architects to derive training algorithms and implement them. - Responsible for collaborating with the verification team to deduce firmware-hardware co-verification plan. - Develop and Debug firmware in RTL based hardware simulations (C Verilog simulations) - Develop and Debug on Silicon bring-up boards. Required Skills: - Good Knowledge of DDR 5 JEDEC spec, knowledge of different DIMM configurations and specifications. - Relevant experience in developing bare-metal firmware for High-speed Ser. Des or Memory interface Physical Layer blocks. - Good Knowledge of C programming language for embedded software development and use of relevant IDE. - Comfortable debugging ...Firmware Engineer, Firmware, Principal, Engineer, Technology