Job Details

Overview

FVCTO - Formal Verification Architect role at Intel Corporation

Who We Are

The Data Center and AI (DCAI) delivers leadership Xeon products to cloud, datacenter and AI customers through development of industry leading IPs that enhances product performance and competitiveness in both Xeon and AI platforms. IP design group within DCAI designs Coherent Fabric IP, Memory controller, NOC, PCIE and many fundamental building blocks for the Xeon server SOCs.

Who You Are

Come join the winning team at FVCTO (Formal Verification Central Tech Office). As a Formal Verification Engineer, you will be responsible the following but not limited to:

• Verify microarchitecture using industry standard Formal Verification tools and technologies based on latest model checking and equivalence checking algorithms on world class design IPs and SOCs for Server, Client and Graphics.
• Use the hardware architecture design and RTL implementation details.
• Define the Formal Verification scope, deploy the right strategy to prove correctness while deploying advanced formal techniques, and create abstraction models for convergence on the design.
• Carve out the right boundaries for the design, create comprehensive formal verification test plans, track, verify, apply abstraction techniques, and converge on complex designs to deliver a high-quality design on schedule and articulate the ROI.
• Analyses new methodologies, evaluates new tools, and corroborates results.
• Work with vendors to resolve hard design and tool problems.

In addition to the qualifications, a successful candidate will demonstrate:

• Problem solving and debugging skills.
• Willingness to work closely with various design teams and cross site teams.
• Verbal and written communication skills.
• Motivated, self- directed and can work effectively both independently and in a team environment.

QualificationsMinimum Qualifications

• Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science or a related field with 9 years relevant experience or schoolwork OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science or a related field with 6 years relevant experience or schoolwork OR PhD in Electrical Engineering, Computer Engineering, Computer Science or a related field with 4 years relevant experience or schoolwork

Experience In The Following

• RTL languages like System Verilog or VHDL Assertion languages like SVA, formal verification.

Preferred Qualifications

• Experience with: The fundamentals of formal verification technology, including model checking and writing formal assertions to express architectural intent of designs
• Formal verification principles and methods
• Computer architecture, digital design and verification methods
• Research in formal verification domain

Job Type

• Experienced Hire

Shift

• Shift 1 (United States of America)

Location

• Primary Location: US, California, Santa Clara

• Additional Locations: US, California, Folsom; US, Oregon, Hillsboro; US, Texas, Austin

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Salary

Annual Salary Range for jobs which could be performed in the US: $177,200.00-$250,160.00. Salary range dependent on a number of factors including location and experience.

Work Model

This role will require an on-site presence. Job posting details (such as work model, location or time type) are subject to change.

Seniority level

• Mid-Senior level

Employment type

• Full-time

Job function

• Design, Art/Creative, and Information Technology

Industries

• Semiconductor Manufacturing

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