Job Details

📌 Job Title: Design Verification Engineer (GPU/CPU Subsystems)

📍 Location: Austin, TX or San Jose, CA. Must be available to work (5) days per week at the client office.

🚀 About the Role

We are looking for a highly skilled Design Verification Engineer to join our semiconductor team. In this role, you will be responsible for verifying complex GPU/CPU subsystems, ensuring high-quality and robust hardware design through advanced verification methodologies.

🔧 Key Responsibilities

• Develop comprehensive verification plans, including goals, coverage metrics, and sign-off criteria aligned with architectural specifications
• Design and build scalable verification environments/testbenches using SystemVerilog, UVM, and C++
• Implement constrained-random testing, coverage-driven verification, and assertion-based methodologies
• Create targeted test scenarios to validate interactions across multiple blocks, interfaces, and data paths
• Debug complex issues across subsystem components, perform root cause analysis, and collaborate with design/architecture teams
• Enhance verification methodologies, tools, and automation for improved efficiency and quality
• Stay updated with latest industry trends and verification technologies

✅ Required Qualifications

• Bachelor's degree in Computer Science/Engineering with 6+ years of experience
• (or Master's with 4+ years / PhD with 2+ years)
• Hands-on experience in GPU, CPU, or advanced semiconductor design verification
• Strong knowledge of computer architecture and subsystem-level design
• Proficiency in SystemVerilog and UVM
• Experience with:
• Constrained-random verification
• Functional coverage
• Assertions
• Strong debugging, analytical, and problem-solving skills

💻 Programming Skills

• Proficient in C/C++
• Experience with Python/Perl is a plus

🤝 Soft Skills

• Excellent communication and collaboration skills
• Ability to work in a fast-paced, global environment
• Comfortable handling ambiguity and complex problem-solving

⭐ Preferred Qualifications

• Experience in subsystem-level verification and coverage closure
• Exposure to multiple block/interface verification strategies

📩 Interested?

Apply now or reach out directly to discuss this opportunity!