Job Details

Company

Qualcomm Technologies, Inc.

Job Area

Engineering Group > ASICS Engineering

General Summary

This individual leads, plans, synthesizes ambiguous or conflicting requirements and performs the complex responsibility of the Physical Design Flow of high-speed DDR, graphics, physical verification flows, micro‑architecture, SOC algorithm design and modeling, and methodology, focusing on target power utilization and optimization for system‑on‑chip (SoC) products and how these features impact power and performance. Responsibilities include:

• Floor Planning
• Clock Tree Synthesis
• Place and Route
• PDN
• Timing analysis and closure

Performs various physical verification checks (such as LVS, DRC, design‑for‑manufacturing & design‑for‑yield) at the chip and block levels. Provides schedules and support cross‑functional engineering effort to drive to signoff closure for tapeout. Acts as a strong contributor at design reviews and project meetings and communicates and implements a development plan.

Qualifications

Will accept a Master's Degree (or foreign academic equivalent) in Electrical Engineering, Computer Engineering, Computer Science or related degree field and three (3) years of experience in a related occupation.

Compensation

$140,000.00 - $210,000.00/year

EEO Employer

Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.